Electrical Transport
with RuCl₃

Ultrafast Nano-Optics Group · UC Berkeley
RuCl₃ TMD Nanofabrication 2D Materials
76 K Measurement Temperature
30 nm hBN Gate Dielectric
~1 MΩ Contact Resistance
4 Device Iterations

Overview

Schottky barriers at graphene–TMD interfaces introduce contact resistance that obscures the intrinsic transport properties of WS₂ and MoSe₂. By depositing multilayer RuCl₃ on graphene contacts, its exceptionally large work function drives interlayer charge transfer — hole-doping graphene to high carrier densities and converting the junction from Schottky to metal-like, enabling accurate electrical transport measurements.

Device Stack

⬛
Top hBN Encapsulant
🔵
Graphene + RuCl₃ Four-terminal contacts via photolithography & plasma etching
🟡
Twisted WS₂ / MoSe₂ Active TMD layer
⬜
hBN Gate Dielectric ~30 nm thickness
⚫
Multilayer Graphite Back gate
⬜
Bottom hBN Substrate

Fabrication

Three device generations were fabricated. Initial dual-gate stacks with twisted WS₂ did not perform as expected due to heterostructure complexity. A simplified single-gate MoSe₂ device was successfully fabricated and measured.

Mono-MoSe₂ dual gate
Fig 1 — Mono-MoSe₂, graphite dual gate
Mono-WS₂ dual gate
Fig 2 — Mono-WS₂, graphite dual gate
Mono-MoSe₂ single gate
Fig 3 — Mono-MoSe₂, single gate ✓ successful

Results

Two-terminal resistance was measured at 76 K as a function of source–drain voltage across three back-gate voltages using a liquid nitrogen dewar.

IV curve Vb=7V
I–V curve, Vβ = 7 V
IV curve Vb=8.5V
I–V curve, Vβ = 8.5 V
IV curve Vb=10V
I–V curve, Vβ = 10 V

Progressive linearization — I–V curves become more symmetric as gate voltage increases, consistent with carrier-density screening of the Schottky barrier.

Residual barrier — Pronounced nonlinearity persists near Vsp = 0 even at 10 V, indicating the Schottky barrier was not fully eliminated.

High contact resistance — ~1 MΩ at Vsp = 1 V, compared to <10⁵ Ω for fully ohmic graphene contacts on WS₂ after annealing (Ovchinnikov et al., ACS Nano 2014).

Dielectric limitation — The 30 nm hBN gate dielectric screens the electric field, restricting achievable carrier density at 10 V.

Next Steps

01

Thinner Gate Dielectric

Replace 30 nm hBN with 10 nm — tripling the electric field at the same gate voltage to access higher carrier densities.

02

VTI Cryostat to 2 K

Low-temperature measurements suppress thermal broadening and more clearly resolve intrinsic contact properties via tunneling diagnostics.

03

Metal Contacts + RuCl₃

Au or Ti/Au contacts with RuCl₃ on top to isolate whether the barrier originates at the graphene–TMD interface.

04

Four-Terminal Measurements

Decouple contact resistance from channel resistance, benchmarking against strict linear I–V across ±2 V at all gate voltages.

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